Transport network standards such as Synchronous Optical Network (SONET) and Synchronous Digital Hierarchy (SDH) are well known in the art for transporting data in communication networks.
The lowest bandwidth, or most granular, “high-order” switching unit of a SONET frame is the STS-1 frame. FIG. 1 is a diagram illustrating an STS-1 frame according to the SONET standard. Each STS-1 frame 100 comprises nine 90-column rows, or 9×90=810 bytes, transmitted in 125 μs. In other words, the frame rate is 51.84 Mbps. The first three columns in the 90-column STS-1 frame are the transport overhead (TOH) columns 102. Each STS-1 frame 100 carries a payload in the synchronous payload envelope (SPE) 104, which in turns carries “low-order” switching units. In SONET, there are four such low-order switching units, known as virtual tributaries. The following table summarizes the frame sizes and rates for these virtual tributaries.
FormatFrameVirtualNumber ofNumber ofRateTributaryRowsColumns(Mbps)  VT1.5931.728VT2942.304VT3963.456VT6912 6.912
Being able to cost-effectively manage bandwidth at the VT level is more advantageous to service providers than at the less granular STS-1 level. For instance, Digital Subscriber Loop (DSL) traffic up to the T1 rate can be mapped onto one VT1.5 tributary and carried inside an STS-1 payload. An STS-1 payload can carry up to 28 VT1.5 tributaries at once. Thus, an STS-1 payload can carry up to 28 DSL connections. Likewise, a 10BaseT Ethernet connection can be mapped onto 7 VT1.5 tributaries, enabling an STS-1 frame to carry up to 4 Ethernet connections. With VT level bandwidth management, the available bandwidth is more efficiently utilized.
FIG. 2 is a diagram illustrating an exemplary tributary time-space switch according to the prior art. The switch 200 grooms traffic from P STS-N input streams to Q STS-N output streams with column granularity in an unrestricted non-blocking fashion. In other words, the time-space switch can connect any available output column to any input column in both space and time.
The time-space switch comprises a switch core 201, a connection map 204, and a controller 205. The switch core 201 comprises two identical buffers, 202 and 203, each capable of storing P rows of STS-N data, or 90PN bytes. Each buffer alternates between being a read buffer and a write buffer for 90N byte cycles such that one buffer is the read buffer while the other is the write buffer.
To achieve the time-space switching function, data is written from the current frame row into the write buffer sequentially according to the write address 208 that is generated by the controller 205. As data from the current row fills the write buffer, data from the previous frame row is read from the read buffer according to the order specified in the connection map 204. The connection map 204 generates the read addresses 209 in response to being indexed by the output column counter 210 from the controller 205.
The switch core 201, which has P input ports and Q output ports, logically has one write port of 8P bits wide 206 and Q read ports of 8 bits wide 207. Physical implementation may limit the number of read ports of each switch core memory module to have fewer than Q read ports, (e.g., K read ports), in which case M=┌Q/K┐ copies of the K-read-port-one-write-port switch core modules are necessary to implement Q read ports for the switch core. Such a switch core requires P×N×M×90×8×2=1440 PNM bits. For instance, an 80 Gbps SONET tributary time-space switch having P=32 STS-48 (N=48) input ports requires 1440PNM=2,211,840M bits for the switch core.